Features
•
Frequency Receiving Range of (3 Versions)
– f
0
= 312.5 MHz to 317.5 MHz or
– f
0
= 431.5 MHz to 436.5 MHz or
– f
0
= 868 MHz to 870 MHz
30 dB Image Rejection
Receiving Bandwidth
– B
IF
= 300 kHz for 315 MHz/433 MHz Version
– B
IF
= 600 kHz for 868 MHz Version
Fully Integrated LC-VCO and PLL Loop Filter
Very High Sensitivity with Power Matched LNA
– ATA5723/ATA5724:
–107 dBm, FSK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3
–113 dBm, ASK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3
– ATA5728:
–105 dBm, FSK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3
–111 dBm, ASK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3
High System IIP3
– –18 dBm at 868 MHz
– –23 dBm at 433 MHz
– –24 dBm at 315 MHz
System 1-dB Compression Point
– –27.7 dBm at 868 MHz
– –32.7 dBm at 433 MHz
– –33.7 dBm at 315 MHz
High Large-signal Capability at GSM Band (Blocking –33 dBm at +10 MHz,
IIP3 = –24 dBm at +20 MHz)
Logarithmic RSSI Output
XTO Start-up with Negative Resistor of 1.5 kΩ
5V to 20V Automotive Compatible Data Interface
Data Clock Available for Manchester and Bi-phase-coded Signals
Programmable Digital Noise Suppression
Low Power Consumption Due to Configurable Polling
Temperature Range –40°C to +105°C
ESD Protection 2 kV HBM, All Pins
Communication to Microcontroller Possible using a Single Bi-directional Data Line
Low-cost Solution Due to High Integration Level with Minimum External Circuitry
Requirements
Supply Voltage Range 4.5V to 5.5V
•
•
•
•
UHF ASK/FSK
Receiver
ATA5723
ATA5724
ATA5728
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Benefits
•
•
•
•
•
Low BOM List Due to High Integration
Use of Low-cost 13 MHz Crystal
Lowest Average Current Consumption for Application Due to Self Polling Feature
Reuse of ATA5743 Software
World-wide Coverage with One PCB Due to 3 Versions are Pin Compatible
9106E–RKE–07/08
1. Description
The ATA5723/ATA5724/ATA5728 is a multi-chip PLL receiver device supplied in an SSO20
package. It has been specially developed for the demands of RF low-cost data transmission sys-
tems with data rates from 1 kBit/s to 10 kBbit/s in Manchester or Bi-phase code. Its main
applications are in the areas of keyless entry systems, tire pressure monitoring systems, teleme-
tering, and security technology systems. It can be used in the frequency receiving range of
f
0
= 312.5 MHz to 317.5 MHz, f
0
= 431.5 MHz to 436.5 MHz or f
0
= 868 MHz to 870 MHz for
ASK or FSK data transmission. All the statements made below refer to 315 MHz, 433 MHz and
868.3 MHz applications.
Figure 1-1.
System Block Diagram
UHF ASK/FSK
Remote control receiver
ATA5723/
ATA5724/
ATA5728
Demod.
PLL
Antenna
VCO
Antenna
IF Amp
PLL
XTO
UHF ASK/FSK
Remote control transmitter
T5750/53/54
1 to 5
Control
Micro-
controller
XTO
Power
amp.
LNA
VCO
2
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
Figure 1-2.
Block Diagram
CDEM
FSK/ASK
Demodulator
and Data Filter
RSSI
Limiter out
RSSI
Dem_out
Data
Interface
DATA
RSSI
SENS
AVCC
AGND
DGND
DVCC
POLLING/_ON
Sensitivity
reduction
Polling Circuit
and Control Logic
IF
Amp.
DATA_CLK
MODE
4. Order
f
0
= 1 MHz
FE
CLK
IC_ACTIVE
LPF
f
g
= 2.2 MHz
Standby
Logic
IF
Amp.
Loop
Filter
XTAL2
XTO
XTAL1
Poly-LPF
f
g
= 7 MHz
f
LC-VCO
:2
or :3
LNAREF
f
LNA_IN
LNAGND
LNA
:2
or :4
f
:128
or :64
3
9106E–RKE–07/08
2. Pin Configuration
Figure 2-1.
Pinning SSO20
SENS
IC_ACTIVE
CDEM
AVCC
TEST1
RSSI
AGND
LNAREF
LNA_IN
1
2
3
4
5
6
7
8
9
ATA5723/
ATA5724/
ATA5728
20 DATA
19 POLLING/_ON
18 DGND
17 DATA_CLK
16 MODE
15 DVCC
14 XTAL2
13 XTAL1
12 TEST3
11 TEST2
LNAGND 10
Table 2-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Description
Symbol
SENS
IC_ACTIVE
CDEM
AVCC
TEST 1
RSSI
AGND
LNAREF
LNA_IN
LNAGND
TEST 2
TEST 3
XTAL1
XTAL2
DVCC
MODE
DATA_CLK
DGND
POLLING/_ON
DATA
Function
Sensitivity-control resistor
IC condition indicator: Low = sleep mode, High = active mode
Lower cut-off frequency data filter
Analog power supply
Test pin, during operation at GND
RSSI output
Analog ground
High-frequency reference node LNA and mixer
RF input
DC ground LNA and mixer
Do not connect during operating
Test pin, during operation at GND
Crystal oscillator XTAL connection 1
Crystal oscillator XTAL connection 2
Digital power supply
Selecting 315 MHz/other versions
Low: 315 MHz version (ATA5723)
High: 433 MHz/868 MHz versions (ATA5724/ATA5728)
Bit clock of data stream
Digital ground
Selects polling or receiving mode; Low: receiving mode, High: polling mode
Data output/configuration input
4
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
3. RF Front-end
The RF front-end of the receiver is a low-IF heterodyne configuration that converts the input sig-
nal into about 1 MHz IF signal with a typical image rejection of 30 dB. According to Figure
Figure
1-2 on page 3
the front-end consists of an LNA (Low Noise Amplifier), LO (Local Oscillator), I/Q
mixer, polyphase low-pass filter and an IF amplifier.
The PLL generates the drive frequency f
LO
for the mixer using a fully integrated synthesizer with
integrated low noise LC-VCO (Voltage Controlled Oscillator) and PLL-loop filter. The XTO (crys-
tal oscillator) generates the reference frequency f
REF
= f
XTO
/2 (868 MHz and 433 MHz versions)
or f
REF
= f
XTO
/3 (315 MHz version). The integrated LC-VCO generates two or four times the
mixer drive frequency f
VCO
. The I/Q signals for the mixer are generated with a divide by two or
four circuit (f
LO
= f
VCO
/2 for 868 MHz version, f
LO
= f
VCO
/4 for 433 MHz and 315 MHz versions).
f
VCO
is divided by a factor of 128 or 64 and feeds into a phase frequency detector and is com-
pared with f
REF
. The output of the phase frequency detector is fed into an integrated loop filter
and thereby generates the control voltage for the VCO. If f
LO
is determined, f
XTO
can be calcu-
lated using the following formula:
f
REF
= f
LO
/128 for 868 MHz band, f
REF
= f
LO
/64 for 433 MHz bands, f
REF
= f
LO
/64 for 315 MHz
bands.
The XTO is a two-pin oscillator that operates at the series resonance of the quartz crystal with
high current but low voltage signal, so that there is only a small voltage at the crystal oscillator
frequency at pins XTAL1 and XTAL2. According to
Figure 3-1,
the crystal should be connected
to GND with two capacitors C
L1
and C
L2
from XTAL1 and XTAL2 respectively. The value of
these capacitors are recommended by the crystal supplier. Due to an inductive impedance at
steady state oscillation and some PCB parasitics, a lower value of C
L1
and C
L2
is normally
necessary.
The value of C
Lx
should be optimized for the individual board layout to achieve the exact value of
f
XTO
and hence of f
LO
. (The best way is to use a crystal with known load resonance frequency to
find the right value for this capacitor.) When designing the system in terms of receiving band-
width and local oscillator accuracy, the accuracy of the crystal and the XTO must be considered.
Figure 3-1.
XTO Peripherals
DVCC
XTAL2
XTAL1
C
L1
TEST3
TEST2
V
S
C
L2
The nominal frequency f
LO
is determined by the RF input frequency f
RF
and the IF frequency f
IF
using the following formula (low-side injection):
f
LO
= f
RF
– f
IF
5
9106E–RKE–07/08
